The present invention generally relates to semiconductor device manufacturing, and more particularly to the fabrication of a III/V semiconductor material on a locally relaxed silicon-germanium (SiGe) layer.
The increasing operating speeds and computing power of microelectronic devices have recently given rise to the need for an increase in the complexity and functionality of the semiconductor structures from which that these devices are fabricated. Hetero-integration of dissimilar semiconductor materials, for example, III/V materials, such as gallium arsenide, gallium nitride, indium aluminum arsenide, and/or germanium with silicon or silicon-germanium substrate, is an attractive path to increasing the functionality and performance of the CMOS platform. In particular, heteroepitaxial growth can be used to fabricate many modern semiconductor devices where lattice-matched substrates are not commercially available or to potentially achieve monolithic integration with silicon microelectronics. Performance and, ultimately, the utility of devices fabricated using a combination of dissimilar semiconductor materials, however, depends on the quality of the resulting structure. Specifically, a low level of dislocation defects is important in a wide variety of semiconductor devices and processes, because dislocation defects partition an otherwise monolithic crystal structure and introduce unwanted and abrupt changes in electrical and optical properties, which, in turn, results in poor material quality and limited performance. In addition, the threading dislocation segments can degrade physical properties of the device material and can lead to premature device failure.
Dislocation defects typically arise in efforts to epitaxially grow one kind of crystalline material on a substrate of a different kind of material, often referred to as “heterostructure,” due to different crystalline lattice sizes of the two materials. This lattice mismatch between the starting substrate and subsequent layer(s) creates stress during material deposition that generates dislocation defects in the semiconductor structure.
Integrating III/V semiconductors on a silicon substrate may be very challenging due to the large lattice constant mismatch between III/V semiconductors (5.6-6.4 Å) and silicon (5.4 Å). Aspect ratio trapping has been used as one way to enable integration of the III/V on silicon.